The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also increased the complexity of processing and manufacturing ICs.
ICs are typically fabricated by processing one or more wafers as a “lot” with using a series of wafer fabrication tools (i.e., “processing tools”). Each processing tool typically performs a single wafer fabrication process on the wafers in a given lot. For example, a particular processing tool may perform layering, patterning and doping operations or thermal treatment. A layering operation typically adds a layer of a desired material to an exposed wafer surface. A patterning operation typically removes selected portions of one or more layers formed by layering. A doping operation typically incorporates dopants directly into the silicon through the wafer surface, to produce p-n junctions. A thermal treatment typically heats a wafer to achieve specific results (e.g., dopant drive-in or annealing). As a result, there is a need for transporting the wafer in the factory.
Although numerous improvements to the methods of transporting wafer have been invented, they have not been entirely satisfactory in all respects. Consequently, it would be desirable to provide a solution to improve the transportation system so as to mitigate or avoid the production of excess scrap wafer due to improper storage conditions for the wafer during its transportation.